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cy22393, cy22394, cy22395 three-pll serial-programmable flash-programmable clock generator cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-07186 rev. *d revised october 10, 2008 features three integrated phase-locked loops (plls) ultra wide divide counters (8-bit q, 11-bit p, and 7-bit post divide) improved linear crystal load capacitors flash programmability with external programmer field-programmable low jitter, high accuracy outputs power management options (shutdown, oe, suspend) configurable crystal drive strength frequency select through three external lvttl inputs 3.3v operation 16-pin tssop package cyclocksrt? software support advanced features 2-wire serial interface fo r in-system configurability configurable output buffer digital vcxo high frequency lvpecl output (cy22394 only) 3.3/2.5v outputs (cy22395 only) benefits generates up to three unique frequencies on up to six outputs from an external source. allows for 0 ppm frequency generation and frequency conversion in the most demanding applications. improves frequency accuracy over temperat ure, age, process, and initial ppm offset. nonvolatile programming enables easy customization, ultra-fast turnaround, performance tweaking, design timing margin testing, inventory contro l, lower part count, and more secure product supply. in addition, any part in the family can be programmed multiple times, which reduces programming errors and provides an easy upgrade path for existing designs. in-house programming of samples and prototype quantities is available using the cy3672 ftg development kit. production quantities are available through cypress semiconductor?s value-added distribution partners or by using third-party programmer s from bp microsystems, hilo systems, and others. performance suitable for high-end multimedia, communica- tions, industrial, a/d converters, and consumer applications. supports numerous low power application schemes and reduces electromagnetic interference (emi) by allowing unused outputs to be turned off. adjust crystal drive strength for compatibility with virtually all crystals. 3-bit external frequency select options for pll1, clka, and clkb. industry standard packaging saves on board space. easy to use software support for design entry. 2-wire serial interface allows in-system programming into volatile configuration memory. all frequency settings can be changed, providing literally millions of frequency options. adjust output buffer strength to lower emi or improve timing margin. fine tune crystal oscillator frequency by changing load capacitance. differential output up to 400 mhz. provides interfacing option for low voltage parts. [+] feedback
cy22393, cy22 394, cy22395 document #: 38-07186 rev. *d page 2 of 19 selector guide part number outputs input frequency range output frequency range specifics cy22393fc 6 cmos 8 mhz?30 mhz (external crystal) 1 mhz?166 mhz (reference clock) up to 200 mhz commercial temperature cy22394fc 1 pecl/ 4 cmos 8 mhz?30 mhz (external crystal) 1 mhz?166 mhz (reference clock) 100 mhz?400 mhz (pecl) up to 200 mhz (cmos) commercial temperature cy22394fi 1 pecl/ 4 cmos 8 mhz?30 mhz (external crystal) 1 mhz?150 mhz (reference clock) 125 mhz?375 mhz (pecl) up to 166 mhz (cmos) industrial temperature cy22395fc 4 lvcmos/ 1 cmos 8 mhz?30 mhz (external crystal) 1 mhz?166 mhz (reference clock) up to 200 mhz (3.3v) up to 133 mhz (2.5v) commercial temperature cy22395fi 4 lvcmos/ 1 cmos 8 mhz?30 mhz (external crystal) 1 mhz?150 mhz (reference clock) up to 166 mhz (3.3v) up to 133 mhz (2.5v) industrial temperature xtalin xtalout s2/suspend sdat sclk shutdown /oe configuration flash osc. xbuf pll1 clke 11-bit p 8-bit q pll2 11-bit p 8-bit q pll3 11-bit p 8-bit q 4x4 switch crosspoint divider /2, /3, or /4 divider 7-bit divider 7-bit divider 7-bit divider 7-bit clka clkb clkc clkd logic block diagram - cy22393 [+] feedback
cy22393, cy22 394, cy22395 document #: 38-07186 rev. *d page 3 of 19 xtalin xtalout s2/suspend sdat sclk shutdown /oe configuration flash osc. xbuf pll1 p+clk 11-bit p 8-bit q pll2 11-bit p 8-bit q pll3 11-bit p 8-bit q 4x4 switch crosspoint divider 7-bit divider 7-bit divider 7-bit pecl output clka clkb clkc p-clk 0o 180o logic block diagram - cy22394 xtalin xtalout s2/suspend sdat sclk shutdown /oe configuration flash osc. pll1 lclke 11-bit p 8-bit q pll2 11-bit p 8-bit q pll3 11-bit p 8-bit q 4x4 switch crosspoint divider 7-bit divider 7-bit divider 7-bit divider 7-bit divider /2, /3, or /4 lclka lclkb clkc lclkd lclka, lclkb, lclkd, lclke referenced to lvdd logic block diagram - cy22395 [+] feedback
cy22393, cy22 394, cy22395 document #: 38-07186 rev. *d page 4 of 19 1 2 3 4 5 6 7 8 9 10 clkc v dd agnd xtalin xtalout xbuf clkd clke shutdown /oe s2/suspend av dd sclk (s1) sdat (s0) gnd clka clkb 16-pin tssop 11 12 13 14 15 16 cy22393 1 2 3 4 5 6 7 8 9 10 clkc v dd agnd xtalin xtalout xbuf p?clk p+ clk shutdown /oe s2/suspend av dd sclk (s1) sdat (s0) gnd clka clkb 16-pin tssop 11 12 13 14 15 16 cy22394 1 2 3 4 5 6 7 8 9 10 clkc v dd agnd xtalin xtalout lclkd lclke shutdown /oe s2/suspend av dd sclk (s1) sdat (s0) gnd/lgnd lclka lclkb 16-pin tssop 11 12 13 14 15 16 cy22395 lv dd pinouts figure 1. pin diagram - 16 -pin tssop cy22393/cy22394/cy22394 pin definitions name pin number cy22393 pin number cy22394 pin number cy22395 description clkc 1 1 1 configurable clock output c v dd 2 2 2 power supply agnd 3 3 3 analog ground xtalin 4 4 4 reference crystal input or external reference clock input xtalout 5 5 5 reference crystal feedback xbuf 6 6 n/a buffered reference clock output lv dd n/a n/a 6 low voltage clock output power supply clkd or lclkd 7 n/a 7 configurable clock output d; lclkd referenced to lvdd p? clk n/a 7 n/a lv pecl output [1] clke or lclke 8 n/a 8 configurable clock ou tput e; lclke referenced to lvdd p+ clk n/a 8 n/a lv pecl output [1] clkb or lclkb 9 9 9 configurable clock ou tput b; lclkb referenced to lvdd clka or lclka 10 10 10 configurable clock ou tput a; lclka referenced to lvdd gnd/lgnd 11 11 11 ground sdat (s0) 12 12 12 serial port data. s0 value latched during start up sclk (s1) 13 13 13 serial port clock. s1 value latched during start up av dd 14 14 14 analog power supply s2/ suspend 15 15 15 general purpose input for frequency control; bit 2. optionally, suspend mode control input shutdown / oe 16 16 16 places outputs in tri-state condition and shuts down chip when low. optionally, only places out puts in tri-state condition and does not shut down chip when low note 1. lvpecl outputs require an external termination network. [+] feedback
cy22393, cy22 394, cy22395 document #: 38-07186 rev. *d page 5 of 19 operation the cy22393, cy22394, and cy22395 are a family of parts designed as upgrades to the existing cy22392 device. these parts have similar performance to the cy22392, but provide advanced features to meet the needs of more demanding applications. the clock family has three plls which, when combined with the reference, allow up to four independent frequencies to be output on up to six pins. these three plls are completely programmable. configurable plls pll1 generates a frequency that is equal to the reference divided by an 8-bit divider (q) and multiplied by an 11-bit divider in the pll feedback loop (p). the output of pll1 is sent to two locations: the cross point switch and the pecl output (cy22394). the output of pll1 is also sent to a /2, /3, or /4 synchronous post-divider that is output through clke. the frequency of pll1 can be changed using serial programming or by external cmos inputs, s0, s1, and s2. see the following section on general purpose inputs for more detail. pll2 generates a frequency that is equal to the reference divided by an 8-bit divider (q) and multiplied by an 11-bit divider in the pll feedback loop (p). the output of pll2 is sent to the cross point switch. the frequency of pll2 is changed using serial programming. pll3 generates a frequency that is equal to the reference divided by an 8-bit divider (q) and multiplied by an 11-bit divider in the pll feedback loop (p). the output of pll3 is sent to the cross point switch. the frequency of pll3 is changed using serial programming. general purpose inputs s2 is a general purpose input that is programmed to allow for two different frequency settings. options that switches with this general purpose input are as foll ows: the frequency of pll1, the output divider of clkb, and the output divider of clka. the two frequency settings are contained within an eight-row frequency table. the values of sclk (s1) and sdat (s0) pins are latched during start up and used as the other two indexes into this array. clka and clkb have seven-bit dividers that point to one of the two programmable settings (register 0 and register 1). both clocks share a single register control and both must be set to register 0, or both must be set to register 1. for example, the part may be programmed to use s0, s1, and s2 (0,0,0 to 1,1,1) to control eight different values of p and q on pll1. for each pll1 p and q setting, one of the two clka and clkb divider registers can be chosen. any divider change as a result of switching s0, s1, or s2 is guaranteed to be glitch free. crystal input the input crystal oscillator is an important feature of this family of parts because of its flexibility and performance features. the oscillator inverter has programmable drive strength. this allows for maximum compatibility with crystals from various manufacturers, process, performance, and quality. the input load capacitors are placed on-die to reduce external component cost. these capacitors are true parallel-plate capacitors for ultra-linear perf ormance. these were chosen to reduce the frequency shift that occurs when nonlinear load capacitance interacts with load, bias, supply, and temperature changes. nonlinear (fet gate) cryst al load capacitors must not be used for mpeg, pots dial tone, communications, or other applications that are sensit ive to absolute frequency requirements. the value of the load capacitors is determined by six bits in a programmable register. the load capacitance can be set with a resolution of 0.375pf for a total crystal load range of 6pf to 30pf. for driven clock inputs, the input load capacitors can be completely bypassed. this allows the clock chip to accept driven frequency inputs up to 166 mhz. if the application requires a driven input, leave xtalout floating. digital vcxo the serial programming interface is used to dynamically change the capacitor load value on the crystal. a change in crystal load capacitance corresponds with a change in the reference frequency. for special pullable crystals specified by cypress, the capacitance pull range is +150 ppm to ?150 ppm from midrange. be aware that adjusting the frequency of the reference affects all frequencies on all plls in a similar manner since all frequencies are derived from the single reference. output configuration under normal operation there ar e four internal frequency sources that are routed thro ugh a programmable cross point switch to any of the four progra mmable 7-bit output dividers. the four sources are: reference, pll1, pll2, and pll3. the following is a description of each output. clka?s output originates from the cross point switch and goes through a programmable 7-bit post divider. the 7-bit post divider derives its value from one of the two programmable registers. see the section on ?general purpose inputs? on page 5 for more information. clkb?s output originates from the cross point switch and goes through a programmable 7-bit post divider. the 7-bit post divider derives its value from one of the two programmable registers. see the section on ?general purpose inputs? on page 5 for more information. clkc?s output originates from the cross point switch and goes through a programmable 7-bit post divider. the 7-bit post divider derives its value from one programmable register. clkd?s output originates from the cross point switch and goes through a programmable 7-bit post divider. the 7-bit post divider derives its value from one programmable register. for the cy22394, clkd is brought out as the complimentary version of a lv pecl clock referenced to clke, bypassing both the cross point switch and 7-bit post divider. clke?s output originates from pll1 and goes through a post divider that may be programmed to /2, /3, or /4. for the cy22394, clke is brought out as a low voltage pecl clock, bypassing the post divider. xbuf is the buffered reference. [+] feedback
cy22393, cy22 394, cy22395 document #: 38-07186 rev. *d page 6 of 19 the clock outputs have been designed to drive a single point load with a total lumped load capacitance of 15 pf. while driving multiple loads is possible with the proper termination it is generally not recommended. power-saving features the shutdown /oe input tri-states the outputs when pulled low. if system shutdown is enabled, a low on this pin also shuts off the plls, counters, reference oscillator, and all other active components. the resulting current on the v dd pins is less than 5 ma (typical). relock the plls after leaving shutdown mode. the s2/suspend input is configured to shut down a customizable set of outputs and/or plls, when low. all plls and any of the outputs are shut off in nearly any combination. the only limitation is that if a pl l is shut off, all outputs derived from it must also be shut off. suspending a pll shuts off all associated logic, while suspending an output simply forces a tri-state condition. with the serial interface, each pll and/or output is individually disabled. this provides total control over the power savings. improving jitter jitter optimization control is useful for mitigating problems related to similar clocks switchi ng at the same moment, causing excess jitter. if one pll is driving more than one output, the negative phase of the pll can be selected for one of the outputs (clka?clkd). this prevents the output edges from aligning, allowing superior jitter performance. power supply sequencing for parts with multiple v dd pins, there are no power supply sequencing requirements. the part is not fully operational until all v dd pins have been brought up to the voltages specified in the operating conditions table on page 13. all grounds must be connected to the same ground plane. cyclocksrt software cyclocksrt is our second generation software application that allows users to configure this family of devices. the easy-to-use interface offers complete contro l of the many features of this family including, but not limited to, input frequency, pll and output frequencies, and different functional options. it checks data sheet frequency range limitations and automatically applies performance tuning. cyclocksrt also has a power estimation feature that allows the user to see the power consumption of a specific configuration. you can download a free copy of cyberclocks that includes cyclocksrt for free on cypress?s web site at www.cypress.com . cyclocksrt is used to generate p, q, and divider values used in serial programming. there are many internal frequency rules that are not documented in this data sheet, but are required for proper operation of the device. check these rules by using the latest version of cyclocksrt. junction temperature limitations it is possible to program this family such that the maximum junction temperature rating is exceeded. the package ja is 115 c/w. use the cyclocksrt power estimation feature to verify that the programmed configuration meets the junction temperature and package power dissipation maximum ratings. dynamic updates the output divider registers are not synchronized with the output clocks. changing the divider val ue of an active output is likely cause a glitch on that output. pll p and q data is spread between three bytes. each byte becomes active on the acknowledge for that byte, so changing p and q data for an active pll is likely cause the pll to try to lock on an out-of-bounds condition. for this reason, turn off the pll being programmed during the update. do this by setting the pll*_en bit low. pll1, clka, and clkb each have multiple registers supplying data. to program these resources safely, always program an inactive register, and then transiti on to that register. this allows these resources to stay active during programming. the serial interface is active even with the shutdown /oe pin low as the serial interface logic uses static components and is completely self timed. the part does not meet the i dds current limit with transitioning inputs. memory bitmap definitions clk{a?d}_div[6:0] each of the four ma in output clocks (cl ka?clkd) features a 7-bit linear output divider. any divider setting between 1 and 127 may be used by programming the value of the desired divider into this register. odd divide va lues are automatic ally duty cycle corrected. setting a divide value of zero powers down the divider and forces the output to a tri-state condition. clka and clkb have two divider registers, selected by the divsel bit (which in turn is selected by s2, s1, and s0). this allows the output divider value to change dynamically. for the cy22394 device, clkd_div = 000001. clke_div[1:0] clke has a simpler divider (see ta b l e 1 ). for the cy22394, set clke_div = 01. table 1. clke divider clke_div[1:0] clke output 00 off 01 pll1 0 phase/4 10 pll1 0 phase/2 11 pll1 0 phase/3 [+] feedback
cy22393, cy22 394, cy22395 document #: 38-07186 rev. *d page 7 of 19 clk*_fs[2:0] each of the four main output clocks (clka?clkd) has a three-bit code that determines the clock sources for the output divider. the available clock sources are: reference, pll1, pll2, and pll3. each pll provides both positive and negative phased outputs, for a total of seven clock sources (see table 2 ). note that the phase is a relative measure of the pll output phases. no absolute phase relation exists at the outputs. xbuf_oe this bit enables the xbuf output when high. for the cy22395, xbuf_oe = 0. pdnen this bit selects the function of the shutdown /oe pin. when this bit is high, the pin is an active low shutdown control. when this bit is low, this pin is an active high output enable control. clk*_acadj[1:0] these bits modify th e output predrivers, changing the duty cycle through the pads. these are nominally set to 01, with a higher value shifting the duty cycle higher. the performance of the nominal setting is guaranteed. clk*_dcadj[1:0] these bits modify the dc drive of the outputs. the performance of the nominal setting is guaranteed. pll*_q[7:0] pll*_p[9:0] pll*_p0 these are the 8-bit q value and 11-bit p values that determine the pll frequency. the formula is: pll*_lf[2:0] these bits adjust the loop filter to optimize the stability of the pll. ta b l e 4 can be used to guarantee stability. however, cyclocksrt uses a more complica ted algorithm to set the loop filter for enhanced jitter performance. use the print preview function in cyclocksrt to determine the charge pump settings for optimal jitter performance. pll*_en this bit enables the pll when high. if pll2 or pll3 are not enabled, then any output select ing the disabled pll must have a divider setting of zero (off). since the pll1_en bit is dynamic, internal logic automatically turns off dependent outputs when pll1_en goes low. divsel this bit controls which register is used for the clka and clkb dividers. osccap[5:0] this controls the internal capacitive load of the oscillator. the approximate effective crystal load capacitance is: set to zero for external reference clock. table 2. clock source clk*_fs[2:0] clock source 000 reference clock 001 reserved 010 pll1 0 phase 011 pll1 180 phase 100 pll2 0 phase 101 pll2 180 phase 110 pll3 0 phase 111 pll3 180 phase table 3. output drive strength clk*_dcadj[1:0] output drive strength 00 ?30% of nominal 01 nominal 10 +15% of nominal 11 +50% of nominal table 4. loop filter settings pll*_lf[2:0] p t min p t max 00016231 001 232 626 010 627 834 011 835 1043 100 1044 1600 f pll f ref p t q t ------ - ?? ?? = p t 2p3 + () () po + = q t q2 + = equation 1 c load 6pf osccap 0.375pf () + = equation 2 [+] feedback
cy22393, cy22 394, cy22395 document #: 38-07186 rev. *d page 8 of 19 oscdrv[1:0] these bits control the crystal o scillator gain setting. these must always be set according to table 5 . the parameters are the crystal frequency, internal crystal parasitic resistance (available from the manufacturer), and the osccap setting during crystal start up, which occurs when power is applied, or after shutdown is released. if in doubt, use the next higher setting. for external reference, the use ta b l e 6 . reserved these bits must be programmed low for proper operation of the device. table 5. crystal oscillator gain settings osccap 00h?20h 20h?30h 30h?40h crystal freq\ r 30 60 30 60 30 60 8?15 mhz 00 01 01 10 01 10 15?20 mhz 01 10 01 10 10 10 20?25 mhz 01 10 10 10 10 11 25?30 mhz 10 10 10 11 11 na table 6. osc drv for external reference external freq (mhz) 1?25 25?50 50?90 90?166 oscdrv[1:0] 00 01 10 11 serial programming bi tmaps ? summary tables addr divsel b7 b6 b5 b4 b3 b2 b1 b0 08h 0 clka_fs[0] clka_div[6:0] 09h 1 clka_fs[0] clka_div[6:0] 0ah 0 clkb_fs[0] clkb_div[6:0] 0bh 1 clkb_fs[0] clkb_div[6:0] 0ch ? clkc_fs[0] clkc_div[6:0] 0dh ? clkd_fs[0] clkd_div[6:0] 0eh ? clkd_fs[2:1] clkc_fs[2:1 ] clkb_fs[2:1] clka_fs[2:1] 0fh ? clk{c,x}_acadj[1:0] clk{a,b,d,e} _acadj[1:0] pdnen xbuf_oe clke_div[1:0] 10h ? clkx_dcadj[1] clk{d,e}_dcadj[ 1] clkc_dcadj[1] clk{a,b}_dcadj[1] 11h ? pll2_q[7:0] 12h ? pll2_p[7:0] 13h ? reserved pll2_en pll2_lf[2:0] pll2_po pll2_p[9:8] 14h ? pll3_q[7:0] 15h ? pll3_p[7:0] 16h ? reserved pll3_en pll3_lf[2:0] pll3_po pll3_p[9:8] 17h ? osc_cap[5:0] osc_drv[1:0] addr s2 (1,0) b7 b6 b5 b4 b3 b2 b1 b0 40h 000 pll1_q[7:0] 41h pll1_p[7:0] 42h divsel pll1_en pll1_lf[2:0] pll1_po pll1_p[9:8] 43h 001 pll1_q[7:0] 44h pll1_p[7:0] 45h divsel pll1_en pll1_lf[2:0] pll1_po pll1_p[9:8] 46h 010 pll1_q[7:0] 47h pll1_p[7:0] 48h divsel pll1_en pll1_lf[2:0] pll1_po pll1_p[9:8] [+] feedback
cy22393, cy22 394, cy22395 document #: 38-07186 rev. *d page 9 of 19 serial bus programming protocol and timing the cy22393, cy22394 and cy22395 have a 2-wire serial interface for in-system progra mming. they use the sdat and sclk pins, and operate up to 400 kbit/s in read or write mode. except for the data hold time, it is compliant with the i 2 c bus standard. the basic write serial format is as follows: start bit; 7-bit device address (da); r/w bit; slave clock acknowledge (ack); 8-bit memory address (ma); ack; 8-bit data; ack; 8-bit data in ma+1 if desired; ack; 8-bit data in ma+2; ack; etc. until stop bit. the basic serial format is illus- trated in figure 3 on page 11. default startup condition for the cy22393/94/95 the default (programmed) condition of each device is generally set by the distributor, who programs the device using a customer specified jedec file produced by cyclocksrt, cypress?s propri- etary development software. parts shipped by the factory are blank and unprogrammed. in this condition, all bits are set to 0, all outputs are tri-stated, and the cr ystal oscillator circuit is active. while users can develop their own subroutine to program any or all of the individual registers as described in the following pages, it may be easier to simply use cyclocksrt to produce the required register setting file. device address the device address is a 7-bit valu e that is configured during field programming. by programming different device addresses, two or more parts are connected to the serial interface and can be independently controlled. the device address is combined with a read/write bit as the lsb and is sent after each start bit. the default serial interface addre ss is 69h, but must there be a conflict with any other devices in your system, this can also be changed using cyclocksrt. data valid data is valid when the clock is high, and can only be transi- tioned when the clock is low as illustrated in figure 4 on page 11. data frame every new data frame is indicated by a start and stop sequence, as illustrated in figure 5 on page 11. start sequence - start frame is indicated by sdat going low when sclk is high. every time a start signal is given, the next 8-bit data must be the device address (seven bits) and a r/w bit, followed by register address (eight bits) and register data (eight bits). stop sequence - stop frame is indicated by sdat going high when sclk is high. a stop frame frees the bus for writing to another part on the same bus or writing to another random register address. acknowledge pulse during write mode the cy22393, cy22394, and cy22395 respond with an acknowledge pulse after every eight bits. to do this, they pull the sdat line low during the n*9 th clock cycle, as illustrated in figure 6 on page 12. (n = the number of bytes transmitted). during read mode, the master generates the acknowledge pulse after the data packet is read. write operations writing individual bytes a valid write operation must have a full 8-bit register address after the device address word from the master, which is followed by an acknowledge bit from t he slave (ack = 0/low). the next eight bits must contain the data word intended for storage. after the data word is received, the slave responds with another acknowledge bit (ack = 0/low), and the master must end the write sequence with a stop condition. 49h 011 pll1_q[7:0] 4ah pll1_p[7:0] 4bh divsel pll1_en pll1_lf[2:0] pll1_po pll1_p[9:8] 4ch 100 pll1_q[7:0] 4dh pll1_p[7:0] 4eh divsel pll1_en pll1_lf[2:0] pll1_po pll1_p[9:8] 4fh 101 pll1_q[7:0] 50h pll1_p[7:0] 51h divsel pll1_en pll1_lf[2:0] pll1_po pll1_p[9:8] 52h 110 pll1_q[7:0] 53h pll1_p[7:0] 54h divsel pll1_en pll1_lf[2:0] pll1_po pll1_p[9:8] 55h 111 pll1_q[7:0] 56h pll1_p[7:0] 57h divsel pll1_en pll1_lf[2:0] pll1_po pll1_p[9:8] addr s2 (1,0) b7 b6 b5 b4 b3 b2 b1 b0 [+] feedback
cy22393, cy22 394, cy22395 document #: 38-07186 rev. *d page 10 of 19 writing multiple bytes to write multiple bytes at a time, the master must not end the write sequence with a stop condition. instead, the master sends multiple contiguous bytes of data to be stored. after each byte, the slave responds with an acknowledge bit, the same as after the first byte, and accept s data until the stop condition responds to the acknowledge bit. when receiving multiple bytes, the cy22393, cy22394, and cy22395 internally increment the register address. read operations read operations are initiated the same way as write operations except that the r/w bi t of the slave address is set to ?1? (high). there are three basic read operations: current address read, random read, and sequential read. current address read the cy22393, cy22394 and cy22395 have an onboard address counter that retains ?1? more than the address of the last word access. if the last word written or read was word ?n?, then a current address read operation returns the value stored in location ?n+1?. when the cy22393, cy22394 and cy22395 receive the slave address with the r/w bit set to a ?1?, they issue an acknowledge and transmit the 8-bit word. the master device does not acknowledge the transfer, but generates a stop condition, which causes the cy22393, cy22394 and cy22395 to stop transmission. random read through random read operations, the master may access any memory location. to perform this type of read operation, first set the word address. do this by sending the address to the cy22393, cy22394 and cy22395 as part of a write operation. after the word address is sent, the master generates a start condition following the acknowledge. this terminates the write operation before any data is stor ed in the address, but not before setting the internal address poin ter. next, the master reissues the control byte with the r/w byte set to ?1?. the cy22393, cy22394 and cy22395 then issue an acknowledge and transmit the 8-bit word. the master device does not acknowledge the transfer, but generates a stop condition which causes the cy22393, cy22394 and cy22395 to stop transmission. sequential read sequential read operations follow the same process as random reads except that the master i ssues an acknowledge instead of a stop condition after transmitting the first 8-bit data word. this action increments the internal address pointer, and subsequently outputs the next 8-bit data word. by continuing to issue acknowl- edges instead of stop conditions, the master serially reads the entire contents of the slave device memory. note that register addresses outside of 08h to 1bh and 40h to 57h can be read from but are not real registers and do not contain configuration information. when the internal address pointer points to the ffh register, after the next increment, the pointer points to the 00h register. figure 2. data transfer sequence on the serial bus sclk start condition sdat stop data may address or acknowledge valid be changed condition [+] feedback
cy22393, cy22 394, cy22395 document #: 38-07186 rev. *d page 11 of 19 figure 3. data frame architecture figure 4. data valid and data transition periods serial programming interface timing figure 5. start and stop frame sdat write start signal device address 7-bit r/w = 0 1 bit 8-bit register address slave 1 bit ack slave 1 bit ack 8-bit register data stop signal multiple contiguous registers slave 1 bit ack 8-bit register data (xxh) (xxh) (xxh+1) slave 1 bit ack 8-bit register data (xxh+2) slave 1 bit ack 8-bit register data (ffh) slave 1 bit ack 8-bit register data (00h) slave 1 bit ack slave 1 bit ack sdat read start signal device address 7-bit r/w = 1 1 bit 8-bit register data slave 1 bit ack slave 1 bit ack stop signal sdat read start signal device address 7-bit r/w = 0 1 bit 8-bit register address slave 1 bit ack slave 1 bit ack 7-bit device stop signal multiple contiguous registers master 1 bit ack 8-bit register data master 1 bit ack (xxh) (xxh) master 1 bit ack 8-bit register data (xxh+1) master 1 bit ack 8-bit register data (ffh) master 1 bit ack 8-bit register data (00h) master 1 bit ack master 1 bit ack current address read address +r/w=1 repeated start bit sdat sclk data valid transition to next bit clk low clk high vih vil t su t dh sdat sclk start transition to next bit stop [+] feedback
cy22393, cy22 394, cy22395 document #: 38-07186 rev. *d page 12 of 19 figure 6. frame format (device address, r/w , register address, register data) serial programming interface timing specifications parameter description min max unit f sclk frequency of sclk ? 400 khz start mode time from sda low to scl low 0.6 ? s clk low sclk low period 1.3 ? s clk high sclk high period 0.6 ? s t su data transition to sclk high 100 ? ns t dh data hold (sclk low to data transition) 100 ? ns rise time of sclk and sdat ? 300 ns fall time of sclk and sdat ? 300 ns stop mode time from sclk high to sdat high 0.6 ? s stop mode to start mode 1.3 ? s sdat sclk da6 da5 da0 r/w ack ra7 ra6 ra1 ra0 ack stop start ack d7 d6 d1 d0 +++ + + + [+] feedback
cy22393, cy22 394, cy22395 document #: 38-07186 rev. *d page 13 of 19 absolute maximum conditions supply voltage................................................?0.5v to +7.0v dc input voltage ........................... ?0.5v to + (av dd + 0.5v) storage temperature ................. .............. ... ?65c to +125c junction temperature ................ .............. .............. ...... 125c data retention at tj=125c..................................> 10 years maximum programming cycles....................................... 100 package power dissipation ...................................... 350 mw static discharge voltage (per mil-std-883, method 301 5) ............... ............ > 2000v latch up (per jedec 17) .................................... > 200 ma stresses exceeding absolute ma ximum conditions may cause permanent damage to the device. these conditions are stress ratings only. functional operation of the device at these or any other conditions beyond thos e indicated in the operation sections of this data sheet is not implied. extended exposure to absolute maximum conditions may affect reliability. operating conditions parameter description part numbers min typ max unit v dd /av dd /lv dd supply voltage all 3.135 3.3 3.465 v lv dd 2.5v output supply voltage cy22395 2.375 2.5 2.625 v t a commercial operating temperature, ambient all 0 ? +70 c industrial operating temper ature, ambient all ?40 ? +85 c c load_out maximum load capacitance all ? ? 15 pf f ref external reference crystal all 8 ? 30 mhz external reference clock, [3] commercial all 1 ? 166 mhz external reference clock, [3] industrial all 1 ? 150 mhz 3.3v electrical characteristics parameter description conditions [2] min typ max unit i oh output high current [4] v oh =(l)v dd ? 0.5, (l)v dd =3.3v 12 24 ? ma i ol output low current [4] v ol = 0.5, (l)v dd =3.3v 12 24 ? ma c xtal_min crystal load capacitance [4] capload at minimum setting ? 6 ? pf c xtal_max crystal load capacitance [3] capload at maximum setting ? 30 ? pf c in input pin capacitance [4] except crystal pins ? 7 ? pf v ih high-level input voltage cmos levels,% of av dd 70% ? ? av dd v il low-level input voltage cmos levels,% of av dd ?30%av dd i ih input high current v in =av dd ?0.3v ? <1 10 a i il input low current v in =+0.3v ? <1 10 a i oz output leakage current three-state outputs ? 10 a i dd total power supply curre nt 3.3v power supply; 2 outputs at 20 mhz; 4 outputs at 40 mhz ?50?ma 3.3v power supply; 2 outputs at 166 mhz; 4 outputs at 83 mhz ?100?ma i dds total power supply current in shutdown mode shutdown active ? 5 20 a notes 2. unless otherwise noted, electrical and switching char acteristics are guaranteed across these operating conditions. 3. external input reference clock must hav e a duty cycle between 40% and 60%, measured at v dd /2. 4. guaranteed by design, not 100% tested. 5. v ddl is only specified and characterized at 3.3v 5% and 2.5v 5%. v ddl may be powered at any value between 3.465 and 2.375. 2.5v electrical characteristics (cy22395 only) [5] parameter description conditions min typ max unit i oh_2.5 output high current [4] v oh =lv dd ? 0.5, lv dd =2.5v 8 16 ? ma i ol_2.5 output low current [4] v ol = 0.5, lv dd =2.5v 8 16 ? ma [+] feedback
cy22393, cy22 394, cy22395 document #: 38-07186 rev. *d page 14 of 19 notes 6. guaranteed to meet 20%?80% output thresholds, duty cycle, and crossing point specifications. 7. reference output duty cycle depends on xtalin duty cycle. 8. jitter varies significantly with configuration. reference output jitter depends on xtalin jitter and edge rate. 3.3v switching characteristics parameter description conditions min typ max unit 1/t 1 output frequency [4, 6] clock output limit, cmos, commercial ? ? 200 mhz clock output limit, cmos, industrial ? ? 166 mhz clock output limit, pecl, commercial (cy22394 only) 100 ? 400 mhz clock output limit, pecl, industrial (cy22394 only) 125 ? 375 mhz t 2 output duty cycle [4, 7] duty cycle for outputs, defined as t 2 t 1 , fout < 100 mhz, divider >= 2, measured at v dd /2 45% 50% 55% duty cycle for outputs, defined as t 2 t 1 , fout > 100 mhz or divider = 1, measured at v dd /2 40% 50% 60% t 3 rising edge slew rate [4] output clock rise ti me, 20% to 80% of v dd 0.75 1.4 v/ns t 4 falling edge slew rate [4] output clock fall time, 20% to 80% of v dd 0.75 1.4 v/ns t 5 output three-state timing [4] time for output to enter or leave three-state mode after shutdown /oe switches ? 150 300 ns t 6 clock jitter [4, 8] peak-to-peak period jitter, clk outputs measured at v dd /2 ?400 ps v 7 p+/p? crossing point [4] crossing point referenced to vdd/2, balanced resistor network (cy22394 only) ?0.2 0 0.2 v t 8 p+/p? jitter [4, 8] peak-to-peak period jitter, p+/p? outputs measured at crossing point (cy22394 only) ?200 ps t 9 lock time [4] pll lock time from power up ? 1.0 3 ms 2.5v switching characteristics (cy22395 only) [5] parameter description conditions min typ max unit 1/t 1_2.5 output frequency [4, 6] clock output limit, lvcmos 133 mhz t 2_2.5 output duty cycle [4, 7] duty cycle for outputs, defined as t 2 t 1 measured at lv dd /2 40% 50% 60% t 3_2.5 rising edge slew rate [4] output clock rise ti me, 20% to 80% of lv dd 0.5 1.0 v/ns t 4_2.5 falling edge slew rate [4] output clock fall time, 20% to 80% of lv dd 0.5 1.0 v/ns [+] feedback
cy22393, cy22 394, cy22395 document #: 38-07186 rev. *d page 15 of 19 switching waveforms figure 7. all outputs, duty cycle and rise and fall time figure 8. output tri-state timing figure 9. cl k output jitter figure 10. p+/p? crossing point and jitter figure 11. cpu frequency change t 1 output t 2 t 3 t 4 t 5 oe all tri-state outputs t 5 clk output t 6 p+ p? v t 8 dd /2 v 7 select cpu old select new select stable f old f new t 9 [+] feedback
cy22393, cy22 394, cy22395 document #: 38-07186 rev. *d page 16 of 19 test circuit figure 12. test circuit 0.1 f av dd 0.1 f (l)v dd clk out c load gnd v dd p+/p- out [+] feedback
cy22393, cy22 394, cy22395 document #: 38-07186 rev. *d page 17 of 19 note 9. not recommended for new designs. ordering information ordering code package type product flow cy22393zc-xxx [9] 16-pin tssop commercial, 0 to 70c cy22393zc-xxxt [9] 16-pin tssop - tape and reel commercial, 0 to 70c cy22393fc [9] 16-pin tssop commercial, 0 to 70c cy22393fct [9] 16-pin tssop - tape and reel commercial, 0 to 70c cy22394fc [9] 16-pin tssop commercial, 0 to 70c cy22394fct [9] 16-pin tssop - tape and reel commercial, 0 to 70c cy22395fc [9] 16-pin tssop commercial, 0 to 70c CY3672-USB ftg programmer cy3698 cy22392f, cy22393f, cy22394f, and cy22395f adapter for CY3672-USB pb-free cy22393zxc-xxx 16-pin tssop commercial, 0 to 70c cy22393zxc-xxxt 16-pin tssop - tape and reel commercial, 0 to 70c cy22393zxi-xxx 16-pin tssop industrial, ?40 to 85c cy22393zxi-xxxt 16-pin tssop - tape and reel industrial, ?40 to 85c cy22393fxc 16-pin tssop commercial, 0 to 70c cy22393fxct 16-pin tssop - tape and reel commercial, 0 to 70c cy22393fxi 16-pin tssop industrial, ?40 to 85c cy22393fxit 16-pin tssop - tape and reel industrial, ?40 to 85c cy22394zxc-xxx 16-pin tssop commercial, 0 to 70c cy22394zxc-xxxt 16-pin tssop - tape and reel commercial, 0 to 70c cy22394zxi-xxx 16-pin tssop industrial, ?40 to 85c cy22394zxi-xxxt 16-pin tssop - tape and reel industrial, ?40 to 85c cy22394fxc 16-pin tssop commercial, 0 to 70c cy22394fxct 16-pin tssop - tape and reel commercial, 0 to 70c cy22394fxi 16-pin tssop industrial, ?40 to 85c cy22394fxit 16-pin tssop - tape and reel industrial, ?40 to 85c cy22395zxc-xxx 16-pin tssop commercial, 0 to 70c cy22395zxc-xxxt 16-pin tssop - tape and reel commercial, 0 to 70c cy22395zxi-xxx 16-pin tssop industrial, ?40 to 85c cy22395zxi-xxxt 16-pin tssop - tape and reel industrial, ?40 to 85c cy22395fxc 16-pin tssop commercial, 0 to 70c cy22395fxct 16-pin tssop - tape and reel commercial, 0 to 70c cy22395fxi 16-pin tssop industrial, ?40 to 85c cy22395fxit 16-pin tssop - tape and reel industrial, ?40 to 85c [+] feedback
cy22393, cy22 394, cy22395 document #: 38-07186 rev. *d page 18 of 19 package diagram figure 13. 16-pin tssop 4.40 mm body z16.173 4.90[0.193] 1.10[0.043] max. 0.65[0.025] 0.20[0.008] 0.05[0.002] 16 pin1id 6.50[0.256] seating plane 1 0.076[0.003] 6.25[0.246] 4.50[0.177] 4.30[0.169] bsc. 5.10[0.200] 0.15[0.006] 0.19[0.007] 0.30[0.012] 0.09[[0.003] bsc 0.25[0.010] 0-8 0.70[0.027] 0.50[0.020] 0.95[0.037] 0.85[0.033] plane gauge dimensions in mm[inches] min. max. reference jedec mo-153 package weight 0.05 gms part # z16.173 standard pkg. zz16.173 lead free pkg. 51-85091-*a [+] feedback
document #: 38-07186 rev. *d revised october 10, 2008 page 19 of 19 cyclocksrt is a trademark of cypress semiconductor. all product a nd company names mentioned in this document are the trademarks of their respective holders. cy22393, cy22 394, cy22395 ? cypress semiconductor corporation, 2001-2008. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products psoc psoc.cypress.com clocks & buffers clocks.cypress.com wireless wireless.cypress.com memories memory.cypress.com image sensors image.cypress.com psoc solutions general psoc.cypress.com/solutions low power/low voltage psoc.cypress.com/low-power precision analog psoc.cypress.com/precision-analog lcd drive psoc.cypress.com/lcd-drive can 2.0b psoc.cypress.com/can usb psoc.cypress.com/usb document title: cy22393/cy22394/cy22395 three-pll seri al-programmable flash-programmable clock generator document number: 38-07186 rev. ecn orig. of change submission date description of change ** 111984 dsg 12/09/01 change from spec number: 38-01144 to 38-07186 *a 129388 rgl 10/13/03 added timing information *b 237755 rgl see ecn added lead-free devices *c 848580 rgl see ecn added references to i 2 c; removed all references to spi *d 2584052 aesa/kvm 10/10/08 updated template. ad ded note ?not recommended for new designs.? added part number cy22393fc, and cy22393fct in ordering information table. removed part number cy22393fi, cy22393fit, cy22393zi-xxx, cy22393zi-xxxt, cy22393fc, cy223 93fct, cy22392fi, cy22392fit, cy22394zc-xxx, cy22394z c-xxxt, cy22394zi-xxx, cy22394zi-xxxt, cy22394fi, cy22394fit, cy22395zc-xxx, cy22395zc-xxxt, cy223 95zi-xxx, cy22395z i-xxxt, cy22395fc, cy22395fct, and cy22395fi in ordering information table. changed lead-free to pb-free. changed serial interface hold time (tdh) from 0ns to 100ns. replaced i 2 c references with ?2-w ire serial interface? [+] feedback

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